a. Field of the Invention
This invention relates to computerized imaging and graphics systems and methods.
b. Related Art
In most imaging and graphics computer systems an image displayed on a video screen is defined by a group of points called pixels. In monochrome line and character displays, for example, each pixel is typically defined by one bit of information which is used to determine whether the pixel is on or off.
In most present day imaging and graphics systems, the pixels are defined by a number of bits which are used to define colors. In many conventional systems, the number of bits used to define each pixel is either four or eight. Four bits will allow sixteen colors to be defined on the video screen, while eight bits will allow 256 colors to be defined.
Some imaging and graphics systems use multiple processors in parallel to increase the number of colors which may be displayed. For example, it may be desired to use a large grey scale along with a spectrum of 256 colors. Also, it may be desirable to define extra bits for use as a graphic or textual overlay. Additional bits may also be desirable for use by various processing hardware. Typically 24 bits are required to display realistic color images, 8 bits for each of the color components red, green and blue. Sophisticated real color systems can also require an extra 8 bits per pixel, used for storing masking and overlay information, giving 32 bits per pixel in total.
A 24 bit system is a typical example of a graphics processing system which is configured to utilize two or more graphics processors in parallel to increase performance. It is common to use complete graphics processors to process each 8 bit component of the 24 bit image. Such a configuration of processors is sometimes referred to as a parallel component processor.
In such a system it is sometimes required that conditions on one or more of the component processors affect the operations occurring in the other processors. A typical example would be a situation where it is desired to check for a specific color across all three processors. Where the specific color is present in the processors frame store (i.e. image memory), the processor posts a logical "1" on its status line. Where the specific color is not present, the processor posts a logical "0". The status bits from the three processors are conventionally placed on a single open collector line of an interprocessor bus and formed into a global interprocessor status.
Those skilled in the art will recognize that open collector schemes will naturally form a logical "AND" of all signals place on a given status line. In other words, if any processor's status bit is low, the interprocessor status line will be forced low. Otherwise, the status line will default to its normally high state.
In the above example, all three processors would monitor the status line and test whether it is high. If all three processors have the same color in a tested memory location, the interprocessor status line will be high. Otherwise it will be low. In this manner, all three processors can know when a given parallel task is complete.
While it is important to be able to know when each internal status bit has gone high, or that one has gone low. Conventional open collector systems limit themselves to being able to detect only those two state of events. For example, graphics processors using conventional open collector technology cannot use a single status line to tell if all of the processors on the bus are posting a low status, or just one. As has been stated, any one processor posting a low on the line will hold the line low.